1. Field of the Invention
The present invention generally relates to electronic circuits, and in particular, to set/reset circuits.
2. Description of the Related Art
A conventional set/reset circuit 100 is shown in FIG. 1, formed by using a pair of cross-coupled NAND gates 102, 104. Alternatively, a pair of cross-coupled NOR gates could have been used. While the circuit 100 may be adequate for supporting a single pair of set and reset input terminals 106, 108, extending this configuration for multiple input pairs would be undesirable. Adding inputs to the circuit 100 would require either stacking transistors in series or using cascaded logic gates, both of which degrade timing performance.
FIG. 2 depicts a schematic diagram of a scalable set/reset circuit 200 formed with cross-coupled inverters 210 to hold the logical state at nodes NSET and NRESET when none of set signal (S0, S1, S2) or reset signal (R0, R1, R2) is asserted. The scalable set/reset circuit 200 includes one set of pull-down transistors 206 coupled to NSET and another set of pull-down transistors 208 coupled to NRESET. Each of the pull-down transistors Q1 through Q6 is stronger than the cross-coupled inverters 210 and is able to overcome the relatively weak inverters 202, 204 to pull a corresponding node (NSET or NRESET) to logical low state.
FIG. 3 depicts a timing diagram for the scalable set/reset circuit 200 shown in FIG. 2, illustrating set and reset operations of the circuit. The output Q of the circuit is initially in a logical low state and the other output Q# is initially in a logical high state. At time T1, a set signal S0 goes high, this low-to-high transition signal asserted to the gate of transistor Q1 turns on the transistor Q1 and pulls the node NSET low at time T2 and the output signal Q high at time T3. The logic low at the node NSET provides logic high at the node NRESET, through inverter 202, at time T4. When NRESET goes high, this causes output Q# to go from high to low at time T5. From time T5 to T6, when neither the set nor reset signal is asserted, the cross-coupled inverters 210 function to hold the state of NSET and NRESET until a reset signal is applied. At T6, a reset signal R0 is applied to the gate of transistor Q2 which causes the transistor Q2 to pull NRESET low at T7 and the output Q# high at time T8. When the logical state of NRESET go from high to low, the inverter 204 will charge the node NSET to high.
While the set/reset circuit 200 of FIG. 2 has an advantage over the circuit 100 of FIG. 1 in that adding a pair of set and reset input terminals only requires the addition of a single pair of transistors to the node NSET and NRESET, one problem associated with the circuit shown in FIG. 2 is that the rise and fall times of the outputs Q and Q# are asymmetric. The rise and fall times of the outputs Q and Q# are inherently mismatched because the cross-coupled inverters 210 are made weaker than the pull-down transistors Q1-Q6 to enable the transistors to overcome the cross-coupled inverters to pull the corresponding node to logical low state. When setting the circuit 200, NSET is pulled low relatively quickly by means of one of the pull-down transistors Q1, Q3, Q5 coupled to NSET. Thus, the low-to-high transition of output Q, in response to a set signal asserted to the gate of one of the pull-down transistors, is relatively quick. When resetting the circuit 200, the node NRESET is pulled low via one of the pull-down transistors Q2, Q4, Q6. This high-to-low transition of NRESET drives the node NSET high through the inverter 202. Because the inverter 202 is a slower device than the pull-down transistors Q2, Q4 or Q6, it will take a while longer to charge the node NSET to high. In this regard, NSET is pulled low much faster than it can be pulled high. This results in the fall time of output Q being greater than the rise time of output Q. This mismatch in rise and fall time of the output can cause problems in applications requiring relatively symmetric rise and fall times of output.